2004Conference Proceedings

  • A. Raychowdhury and K. Roy, "A Circuit Model for Carbon Nanotube Interconnects: Comparative Study with Cu Interconnects for Scaled Technologies" Proc. Of the International Conference on Computer Aided Design (ICCAD), San Jose, Nov 2004, pp: 237-240.
  • A. Raychowdhury and K. Roy, "Circuit Modeling of Carbon Nanotube Interconnects and their Performance Estimation in VLSI Design" Proc. Of the International Workshop on Computational Electronics (IWCE), West Lafayette, Oct 2004.
  • A. Raychowdhury and K. Roy, "Carbon Nanotubes as Interconnects of the Future: A Circuit Perspective" Proc. of the Advanced Metallization Conference, San Diego, Oct 2004.
  • J. Jain, C.-K. Koh, and V. Balakrishnan, "Fast Simulation of VLSI Interconnects" International Conference on Computer Aided Design, San Jose, CA, November 2004, to appear.
  • A. Raychowdhury and K. Roy, "Modeling and Analysis of Carbon Nanotube Interconnects for High Speed VLSI Design" Proc. of the Fourth IEEE Nano Conference, Munich, Aug. 2004, WE-P-37.
  • A. Raychowdhury, J. Guo, K. Roy, and M. Lundstrom, "Choice of Flat-Band Voltage, VDD and Diameter of Ambipolar Schottky-Barrier Carbon Nanotube Transistors in Digital Circuit Design" Proc. of the Fourth IEEE Nano Conference, Munich, Aug. 2004, TH-2-2-1.
  • M.-E. Hwang, A. Raychowdhury, and K. Roy, "Effectiveness of Energy Recovery Techniques in Reducing On-Chip Power Density in Molecular Nano-Technologies" Proc. of the International Symposium on Circuits and System (ISCAS), Vancouver, May 2004, vol. 3, pp-709-712.
  • C. M. Jeffery, A. Basagalar, and R. J. O. Figueiredo, "Dynamic Sparing and Error Correction Techniques for Fault Tolerance in Nanoscale Memory Structures" to be published in the Proceedings of 4th IEEE Conference on Nanotechnology (IEEE-Nano), Munich, German, August 2004.
  • B. A. Davis, J. C. Principe, and J. A. B. Fortes, "Design and Performance Analysis of a Novel Nanoscale Associative Memory" to appear Proc. Of the 4th IEEE Conference on Nanotechnology, August 2004.
  • M.-E. Hwang, A. Raychowdhury, and K. Roy, "Effectiveness of Energy Recovery Techniques in Reducing On-Chip Power Density in Molecular Nano-Technologies" Proc. Of International Symposium on Circuits and System (ISCAS), Vancouver, May 2004.
  • A. Raychowdhury and K. Roy, "A Novel Multiple-Valued Logic Design Using Ballistic Carbon nanotube FETs" Proc. Of the 34th International Symposium on Multi-Valued Logic (ISMVL), Toronto, May 2004, pp-14-19.
  • X. Wu, V. Taylor, J. Geisler, R. Stevens, "Isocoupling: Reusing Kernal Coupling Values to Predict the Performance of Parallel Applications" accepted for presentation at the 18th International Parallel & Distributed Processing Symposium, Santa Fe, New Mexico, April 28, 2004.